Integrated circuit memory devices, such as dynamic random access memories (DRAMs) and static random access memories (SRAMs) undergo testing by the manufacturer during production and often by the end user, for example, in a memory test conducted during computer initialization. As densities of the memory device increase, so that individual IC's are capable of storing sixteen or more megabits of information, the time necessary for testing the IC's increases as well.
In addition, there is an increased interest in providing parts which are fully characterized prior to packaging. This is desired not only because of the cost of the package, but also because there is demand for multi-chip modules (MCMs), in which multiple parts in die form are tested and assembled into a single unit. While there are various techniques purposed for testing, burning in and characterizing a singulated die, it would be advantageous to be able to "wafer map" the die prior to assembly with as many performance characteristics as possible. Ideally, one would want to be able to map the wafer with full device characterization.
MCMs create a particular need for testing prior to assembly, as contrasted to the economics of testing parts which are discretely packaged as singulated parts. For discretely packaged parts, if the product yield of good parts from preliminary testing to final shipment (probe-to-ship) is, for example, 95%, one would not be particularly concerned with packaging costs for the failed parts, if packaging costs are 10% of the product manufacturing costs. Even where packaging costs are considerably higher, as in ceramic encapsulated parts, testing unpackaged die is economical for discretely packaged parts when the added costs approximates that of cost of packaging divided by yield: ##EQU1## where
C=cost
C.sub.DIE =manufacturing cost of functional die
C.sub.ADDL.KGD =additional cost of testing unpackaged die in order to produce known good die (KGD)
Note that in the case of discretely packaged parts, the cost of the die (C.sub.DIE) is essentially not a factor. This changes in the case of MCMs: ##EQU2## Note that again C.sub.DIE is not a factor in modules having identical part types; however, the equation must be modified to account for varied costs and yields of die in modules with mixed part types.
With MCMs, the cost of packaging a failed part is proportional to the number of die in the module. In the case of a .times.16 memory array module, where probe-to-ship yield of the die is 95%, the costs are: ##EQU3## so the additional costs of testing for known good die (KGD) may be 16 times the cost of testing after assembly of an unrepairable module in order to be economical. This, of course, is modified by the ability to repair some failed modules.
One of the test procedures which is used to determine the viability of semiconductor integrated circuits is burnin. In the burnin procedure, the parts are exercised for a period of time with different temperature cycles, including at elevated temperatures. This procedure provides an indication of the operation of the device at the different operating temperatures, and also results in a determination of early part failures. During the burnin process, such early failures, known as "infant mortality," is predicted to occur within a particular amount of time. Therefore, if it can be determined that almost all such failures occur within the first 48 hours of burnin testing, then the burnin test can be completed within that time period. Such factors as temperature, process and device type influence when failures stop happening, so the specific burnin time period will vary with part type and other factors. In the case of testing of packaged discrete devices, each device is able to be separately monitored by external test equipment, so that the external test equipment can be used to provide an indication of the time of failure of that particular part.
In testing die prior to encapsulation, temporary electrical connection must be effected between the die and a fixture. This is accomplished in the bond region, either at the bondpads or closely adjacent the bondpad. In the case of wirebond die, the bondpads is often produced at a level which is not raised above the top surface of the die and may be recessed below the top surface.
One process which causes the top of the bondpads to be recessed is one in which the bondpads are formed, but not formed with raised topography, followed by the formation of a passivation layer. The bondpads are left exposed through the passivation layer, but are recessed below the top of the passivation layer. During wirebonding, the recessed position of the bondpads is inconsequential, but this can create a problem with other attachment techniques. If the die are to be tested prior to encapsulation, the die must be compatible with both the test attachment and the later permanent attachment, and the test attachment must not damage the die in such a way as to inhibit permanent attachment.
In a prior art technique, raised conductive portions of conductive layers could be formed by photoplating. The raised portion is a bump which is used as an electrical contact so that, when a plate is brought into contact with a semiconductor die, the bump engages a bondpad on the die. This contact of the bump with the bondpad on the die presents two problems; dimensional accuracy and distortion.
The raised portions engage diebond pads on the die and the raised portion is compressed against the diebond pads. Subsequent to the raised portion being used, it may be desired to separate the conductive layer, and thereby disconnect the connector from the diebond pads on the die. At this point, the raised portions have been compressed and are unsuitable for reuse without being reformed.
When the bump is used as an electrical contact to engage a bondpad on a semiconductor die, dimensional accuracy is a requisite. Bondpads on semiconductors are made small (approximately 100.mu.) in order to conserve useful surface area, known as "real estate," on the die. In the case of wirebonded die, the size of the bondpad is usually selected to be sufficient to permit a wirebonder to reliably establish wirebond connections to the die. Other connection techniques, such as TAB, have their own requirements, but the bondpads are similarly restricted in size.
The bondpads used in wirebonded die are usually recessed below a passivation layer. The passivation layer is a film of insulator, such as BPSG, and can form a barrier to effective contact of the bump with the bondpad if the bump is too large or is out of alignment.
Other techniques include ball bonding, in which wirebonding techniques are used to deposit a small amount of material on a conductive portion. Rather than permitting a wire to remain attached to the bondsite, sufficient energy is applied to the wirebonder to cause the wire to break from the bondsite, thereby leaving an attached portion of the wire, known as a ball bond. The material for this process must of course be selected in order to permit the process to be properly implemented.
In a prior art technique, raised conductive portions of conductive layers could be formed by a process known as doinking. In doinking, a raised portion of conductive material is formed from material by bringing a probe in close proximity to the material and applying energy to the material. In the preferred embodiment, the probe has a center opening and the applied energy is a combination of thermal energy and ultrasonic mechanical vibration of the probe. The process, known as doinking, uses ultrasonic forging and results in a doink, which consists of a raised portion of the material, surrounded by a crater.